Weaver D.L. (ed.) OpenSPARC Internals

Электронное издание SUN Microsystems, Санта-Клара, Калифорния, США, 2008 год 392 стр. Язык: англ.Содержание:
Introducing Chip Multithreaded (CMT) Processors
OpenSPARC Designs
Academic Uses for OpenSPARC
Commercial Uses for OpenSPARC
Architecture Overview
The UltraSPARC Architecture
Processor Architecture
nteger Unit (IU)
Floating-Point Unit (FPU)
nstructions
Traps
Chip-Level Multithreading (CMT)
OpenSPARC T1 and T2 Processor Implementations
General Background
OpenSPARC T1 Overview
OpenSPARC T1 Components
OpenSPARC T2 Overview
OpenSPARC T2 Components
Summary of Differences Between OpenSPARC T1 and OpenSPARC T2
OpenSPARC T2 Memory Subsystem — A Deeper Look
Caches
Memory Controller Unit (MCU)
Memory Management Unit (MMU)
Noncacheable Unit (NCU)
System Interface Unit (SIU)
Data Management Unit (DMU)
Memory Models
Memory Transactions
OpenSPARC Processor Configuration
Selecting Compilation Options in the T1 Core
Changing Level-1 Cache Sizes
Changing Number of Threads
Removing the Floating-Point Front-End Unit (FFU)
Adding a Second Floating-Point Unit to the OpenSPARC T2 Core.
Changing Level-2 Cache Sizes
Changing the Number of Cores on a Chip
Cookbook Example 1: Integrating a New Stall Signaller Into the T1 Thread Scheduler
Cookbook Example 2: Adding a Special ASI to the T1 Instruction Set
OpenSPARC Design Verification Methodology
erification Strategy
Models
erification Methods
Simulation Verification
Formal Verification
Emulation Verification
Debugging
Post-Silicon VerificationOperating Systems for OpenSPARC T1
rtualization
sun4v Architecture
SPARC Processor Extensions
Operating System Porting
Tools for Developers
Compiling Code
Exploring Program Execution
Throughput Computing
System Simulation, Bringup, and Verification
SPARC Architecture Model
System Configuration File
SAM Huron Sim Architecture
Creation of a Root Disk Image File
Debugging With SAM
Cycle-Accurate Simulation
erification by Cosimulation
OpenSPARC Extension and Modification—Case Study
Overview: OpenSPARC T1/ T2 Source Code and Environment Setup
OpenSPARC T1 Hardware Package
OpenSPARC T2 Hardware Package
Setup for an OpenSPARC Environment
Overview of OpenSPARC T1 Design
SPARC Core
L2 Cache
Memory Controller
I/O Bridge
Floating-Point Unit (FPU)
Bus Interface
Overview of OpenSPARC T2 Design
OpenSPARC T2 Design and Features
SPARC Core
L2 Cache
Cache Crossbar
Memory Controller Unit
Noncacheable Unit (NCU)
Floating-Point and Graphics Unit (FGU)
Trap Logic Unit (TLU)
Reliability and Serviceability
Reset
Performance Monitor Unit (PMU)
Debugging Features
Test Control Unit (TCU)
System Interface Unit (SIU)
OpenSPARC T1 Design Verification Suites
OpenSPARC T1 Verification Environment
Regression Tests
Verification Code
PLI Code Used for the Testbench
Verification Test File Locations
Compilation of Source Code for Tools
Gate-Level Verification
OpenSPARC T2 Design Verification Suites
System Requirements
OpenSPARC T2 Verification Environment
Regression Tests
PLI Code Used For the Testbench
Verification Test File Locations
OpenSPARC Resources
OpenSPARC Terminology