Springer / Kluwer Academic Publishers, 2003. — 417 p. — ISBN: 978-1-4615-0461-0.
The International Technology Roadmap for Semiconductors (ITRS) projects that by 2011 over one billion transistors will be integrated into a single monolithic die. The wiring system of this billion-transistor die will deliver power to each transistor, provide a low-skew synchronizing clock to latches and dynamic circuits, and distribute data and control signals throughout the chip. The resulting design and modeling complexity of this GSI multilevel interconnect network is enormous such that over 1017 coupling inductances and capacitances throughout a nine-to-ten-Ievel metal stack must be managed. This book will address the limits and opportunities for GSI interconnect design and technology in the twenty-first century.
This book is the cumulative effort from academic researchers at Georgia Tech, MIT, and Stanford, as well as from industry researchers at IBM T.J. Watson Research Center, LSI Logic, and SUN microsystems. The material found in this book is unique in that it spans IC interconnect topics ranging from IBM's revolutionary copper process to an in depth exploration into interconnect-aware computer architectures. This broad swath of topics presented by leaders in the research field is intended to provide a comprehensive perspective on interconnect technology and design issues so that the reader will understand the implications of the semiconductor industry's next substantial milestone - gigascale integration.
Interconnect Opportunities for GSI
Cu BEOL Interconnects for Silicon CMOS Logic Technology
Interconnect Parasitic Extraction of R, C, and L
Distributed RC and RLC Transient Models
Power, Clock, and Global Signal Distribution Techniques
Stochastic Multilevel Interconnect Modeling & Optimization
Interconnect-Centric Computer Architectures
Chip-to-Module Interconnect
3-D IC DSM Interconnect Performance Modeling & Analysis
Silicon Microphotonics.