Garrou P., Koyanagi M., Ramm P. (Eds.) Handbook of 3D Integration: 3D Process Technology. Volume 3

Wiley, 2014. — 474 p. — ISBN: 978-3-527-67013-0.Edited by key figures in 3D integration and written by top authors from high-tech companies and renowned research institutions, this book covers the intricate details of 3D process technology. As such, the main focus is on silicon via formation, bonding and debonding, thinning, via reveal and backside processing, both from a technological and a materials science perspective. The last part of the book is concerned with assessing and enhancing the reliability of the 3D integrated devices, which is a prerequisite for the large-scale implementation of this emerging technology.
Invaluable reading for materials scientists, semiconductor physicists, and those working in the semiconductor industry, as well as IT and electrical engineers.3D IC Integration Since 2008
Key Applications and Market Trends for 3D Integration and Interposer Technologies
Economic Drivers and Impediments for 2.5D/3D Integration
Interposer Technology
TSV Formation Overview
TSV Unit Processes and Integration
TSV Formation at ASET
Laser-Assisted Wafer Processing: New Perspectives in Through-Substrate Via Drilling and Redistribution Layer Deposition
Temporary Bonding Material Requirements
Temporary Bonding and Debonding – An Update on Materials and Methods
ZoneBOND: Recent Developments in Temporary Bonding and Room-Temperature Debonding
Temporary Bonding and Debonding at TOK
The 3M Wafer Support System (WSS)
Comparison of Temporary Bonding and Debonding Process Flows
Thinning, Via Reveal, and Backside Processing – Overview
Backside Thinning and Stress-Relief Techniques for Thin Silicon Wafers
Via Reveal and Backside Processing
Dicing, Grinding, and Polishing
Overview of Bonding and Assembly for 3D Integration
Bonding and Assembly at TSMC
TSV Packaging Development at STATS ChipPAC
Cu–SiO2 Hybrid Bonding
Bump Interconnect for 2.5D and 3D Integration
Self-Assembly Based 3D and Heterointegration
High-Accuracy Self-Alignment of Thin Silicon Dies on Plasma-Programmed Surfaces
Challenges in 3D Fabrication
Cu TSV Stress: Avoiding Cu Protrusion and Impact on Devices
Implications of Stress/Strain and Metal Contamination on Thinned Die
Metrology Needs for 2.5D/3D Interconnects.