Yiu Joseph. System-on-Chip Design with Arm Cortex-M Processors

Cambridge: Arm Education Media, 2019. — 333 p. — ISBN: 9781911531197.Right now, you are probably surrounded by Arm processors without even knowing they are there. More than 100 billion chips containing an Arm processor have been produced up to now – this is 13 for every human on the planet ! The most surprising thing is that Arm does not produce chips. It just designs the technology and enables its partners to manufacture differentiated devices that integrate them. Many more of those chips, also called SoCs (system-on-chip), are expected to be produced in the coming years. We even start talking about trillions of devices for the Internet of Things (IoT). Of the total number of SoCs currently out in the market, the great majority use the smallest processors in the Arm product range: the Cortex-M series. Small, very energy efficient and powerful enough for many applications, they are at the heart of many of today’s electronic devices. This book is here to explain how SoCs based on the Arm Cortex-M processor portfolio cores are designed, detail the different elements that compose such a system, explain the different design issues, describe the integration into systems, and discuss how these SoCs are programmed.Foreword Preface Example Codes and Projects / Disclaimer / A note about the scope of this book.
About the Author.Introduction to Arm Cortex-M.
Why learn Cortex-M system design?
Starting Cortex-M system design is easy.
Cortex-M processor systems on FPGA.
Security by design is made easier with Arm architecture.
Understanding different types of Arm processors.
Cortex-M deliverables.
Licensing through Arm Flexible Access and Arm DesignStart.
Obfuscated Verilog – DesignStart Eval.
Verilog RTL sources – DesignStart Pro.
FPGA Packages – DesignStart FPGA.
Documentation.
Introduction to system design with Cortex-M processors.
Overview of Cortex-M Processors.
What memories are needed?
Overview of memories.
Memory declarations in FPGA design tools.
Memory handling in ASIC designs.
Memory endianness.
Defining the peripherals.
Memory map definition.
Bus and memory system design.
TCM integration.
Cache integration.
Defining the processor’s configuration options.
Interrupt signals and related areas.
Event interface.
Clock generation.
Reset generation.
SysTick.
Debug integration.
Power management features.
Top-level pin assignment and pin multiplexing.
Miscellaneous signals.
Sign off requirements.
AMBA, AHB, and APB.
What is AMBA?
Introduction to Advanced Microcontroller Bus Architecture.
History of AMBA.
Various versions of AMBA specification.
Overview of AHB.
Various versions of AHB.
AHB signals.
Basic operations.
Minimal AHB systems.
Handling of multiple bus masters.
More details on the AHB protocol.
Address phase signals.
Data phase signals.
Legacy arbiter handshake signals.
Exclusive access operations.
Introduction to exclusive accesses.
AHB5 exclusive access support.
Mapping of Cortex-M3/M4/M7 exclusive access signals to AHB.
AHB5 TrustZone support.
Overview of APB.
Introduction to the APB bus system.
APB signals and connection.
Additional signals in APB protocol v.
Data values on APB.
Mixing different versions of APB components.
Building simple bus systems for Cortex-M processors.
Introduction to the basics of bus design.
Building a simple Cortex-M0 system.
Building a simple Cortex-M0+ system.
Building a simple Cortex-M1 system.
Building a simple Cortex-M3/Cortex-M4 system.
Handling multiple bus masters.
Exclusive access support.
Address remap.
AHB- based memory connection versus TCM.
Handling of embedded flash memories.
IP requirements.
Flash programming.
Bringing up a new device without a valid program image.
Debug integration with Cortex-M processor systems.
Overview of debug and trace features.
CoreSight Debug Architecture.
Introduction to Arm CoreSight.
Debug connection protocols.
Debug connection concept - Debug Access Port (DAP).
Various arrangements of debug interface structure.
Trace connection concept.
Timestamp.
Debug components discovery (ROM table and component IDs).
Debug authentication.
Debug power request.
Debug reset request.
Cross Trigger Interface.
Debug integration.
JTAG / Serial Wire Debug connections.
Trace port connections.
Clocks for the debug and trace system.
Multi-drop serial wire support.
Debug authentication.
Other related topics.
Other signal connections.
Daisy chain of JTAG connection.
Low-power support.
Overview of low-power Cortex-M features.
Low-power design basics.
Cortex-M low-power interfaces.
Sleep status and GATEHCLK output.
Q-channel low-power interface (Cortex-M23, Cortex-M33, Cortex-M35P).
Sleep hold interface.
Wakeup Interrupt Controller (WIC).
SRPG’s impact on software.
Software power-saving approach.
Cortex-M processor characteristics that enable low-power designs.
High code density.
Short pipeline.
Instruction fetch optimizations.
System-level design considerations.
Low-power designs overview.
Clock sources.
Low-power memories.
Caches.
Low-power analog components.
Maximizing clock gating opportunities.
Sleep mode that completely powers down the processor.
Design of bus infrastructure components.
Overview of a simple AMBA system design.
Typical AHB slave design rules.
Typical AHB infrastructure components.
AHB decoders.
Default slave.
AHB Slave multiplexer.
ROM and RAM with AHB interface.
AHB to APB Bridge.
Bridging from Cortex-M3/Cortex-M4 AHB Lite to AHB.
Design of simple peripherals.
Common practices for peripheral designs.
Designing Simple APB Peripherals.
General Purpose Input Output (GPIO) interface.
Simple APB Timer.
Simple UART.
ID registers.
Other peripheral design considerations.
Security of system control functions.
Processor’s halting.
Handling of 64-bit data.
Putting the system together.
Creating a simple microcontroller-like system.
Design partitioning.
What is inside a simulation environment?
Prepare the minimal software support for simulation.
Overview of example code based on CMSIS-CORE.
Device header file for example MCU (cm3_mcu.h).
Device start-up file for example MCU (startup_cm3_mcu.s).
UART utilities 212 9.4.5 System initialization function.
Retargeting.
Other software support package considerations.
System-level simulation.
Compiling hello world.
Using Modelsim/QuestaSim to compile and simulate the design.
Advanced processor systems and Corstone Foundation IP.
Verification.
ASIC implementation flow.
Design for Testing/Testability (DFT).
Beyond the processor system.
Clock system design.
Clock system design overview.
Clock switching.
Low-power considerations.
DFT considerations.
Multiple power domains and power gating.
Arm processors in a mixed-signal world.
Convergence of microcontrollers and mixed-signal designs.
Analog to digital conversions.
Digital to analog conversions.
Other analog interface approaches.
Connecting ADC and DAC IPs into a Cortex-M system.
Bring an SoC to life – Beetle test chip case study.
Beetle test chip overview.
Beetle test chip challenges.
Beetle test chip system design.
Implementation of the Beetle test chip.
Other related tasks.
Software Development.
Introduction to CMSIS (Cortex Microcontroller Software Interface Standard).
Creating software support for multiple toolchains.
What is needed for creating multiple toolchain support?
Compilation with Arm Compiler.
Compilation with gcc.
Introduction of the Arm Development Studio featuring Arm Keil Microcontroller Development Kit (MDK).
Overview of Keil MDK.
Keil MDK Installation.
Create an application.
Using the project wizard to create a project.
Create and add source files.
Edit the source files.
Defining project options.
Compile the project.
Download and debug the application.
Using ITM for text message output (printf).
Software development in collaborative environments.
Using an RTOS.
RTOS software concepts.
Using Keil RTX.
Optimizing memory usage.
The need for RAM usage analysis.
Configure RTX for stack watermarking.
RTX RTOS viewer in Watch windows.
Other toolchains.
Glossary of terms.