Markulic N., Raczkowski K., Craninckx J., Wambacq P. Digital Subsampling Phase Lock Techniques for Frequency Synthesis and Polar Transmission

New York: Springer, 2019. — 156 p.Wireless technology systems have intruded in almost every aspect of today’s communication. Technology scaling and innovation in the field of integrated circuits (ICs) nurture this wireless revolution, while the need for higher data throughput continues to grow. These trends unfold a severe challenge: in today’s over-allocated spectrum, its efficient use becomes absolutely essential.
In the heart of every transceiver lies a local oscillator (LO), typically implemented as a phase-locked loop (PLL). Crucial aspects of the LO synthesizer are its phase noise and spurious performance. These impose the fundamental limitation for efficient transmit and receive modes; hence, a considerable amount of energy and chip area are typically spent to minimize them. Moreover, in modern systems, the PLL is often used for phase modulation, within digitally intensive polar architectures. For spectrally pure and efficient operation, the digital-to-transmitted output conversion cannot be bandwidth limited or compromised by nonlinearities.
The book starts with an introductive overview of modern frequency synthesis techniques, delivering the basic operation theory in an intuitive fashion, with practical implementation in mind. A point of attention is in this context brought to recent subsampling architectures. These architectures overcome the performance boundaries typically encountered in classical implementations and have potential for redefining today’s state of the art. The following chapters, built around three 28 nm bulk CMOS IC prototypes, explore this idea and present new, performance-leading PLL and polar transmitter designs.