Cao Yu. Predictive Technology Model for Robust Nanoelectronic Design

Springer Science+Business Media, LLC, 2011. — 185 p.The minimum feature size of CMOS technology will approach 10 nm in 10 years.
Such aggressive scaling will lead to wonderful benefits to consumers, businesses and the global society. Unfortunately, it will also lead to increased power dissipation, process variations and device drift, posing tremendous new challenges to designing robust circuits. Already, the design complexity and time are increasing at accelerating rates. The lure of early market entry pushes advanced design research to begin much earlier than the completion of device technology development. The need is even clearer where new devices, e.g. FinFET and post-silicon devices are involved. The concept of technology/circuit co-development is no longer just a good idea, it is a necessity.