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Vandenbussche J., Gielen G., Steyaert M. Systematic Design of Analog IP Blocks

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Vandenbussche J., Gielen G., Steyaert M. Systematic Design of Analog IP Blocks
Springer US, 2003. — 193 p. — ISBN: 978-1-4757-3707-3.
Systematic Design of Analog IP Blocks introduces a design methodology that can help to bridge the productivity gap. Two different types of designs, depending on the design challenge, have been identified: commodity IP and star IP. Each category requires a different approach to boost design productivity. Commodity IP blocks are well suited to be automated in an analog synthesis environment and provided as soft IP. The design knowledge is usually common knowledge, and reuse is high accounting for the setup time needed for the analog library. Star IP still changes as technology evolves and the design cost can only be reduced by following a systematic design approach supported by point tools to relieve the designer from error-prone, repetitive tasks, allowing him/her to focus on new ideas to push the limits of the design.
To validate the presented methodologies, three different industrial-strength applications have been selected and designed accordingly.
Abbreviations.
Introduction
.
Moore’s law and the ITRS roadmap revisited.
Bridging the productivity gap.
Goals of this work.
Outline of this work.
Design Methodologies for analog IP.
Used terminology.
The analog design process.
Overview of Analog Design Automation.
Commodity IP vs. star IP.
The Mondriaan toolset.
Conclusions.
Systematic Design of a Particle Detector Front-End.
PDFE design flow.
PDFE architecture.
Behavioral modeling for system-level specification phase.
PDFE Design phase.
Layout.
Extracted model for verification.
Experimental results.
Conclusions.
Systematic Design of CMOS Current-Steering D/A converters.
D/A converter Design Flow.
Current-steering D/A converter architecture.
Behavioral Modeling for the Specification Phase.
Design Phase.
Layout Generation.
Extracted (A)HDL model for verification.
Experimental Results.
A 12-bit 200 MS/s CMOS D/A converter.
A 14-bit 150 MS/s Q2 Random Walk CMOS D/A converter.
Conclusions on D/A converter Methodology.
Systematic Design of an Interpolating/Averaging A/D Converter.
High-speed A/D converter architectures.
A/D Converter Design Flow.
The interpolating/averaging architecture.
Behavioral Modeling for the Specification Phase.
Design phase.
Layout.
Verification Phase.
Experimental Results.
Conclusions.
General Conclusions.
Bibliography
.
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