Jhan Y.-R., Wu Y.-C. 3D TCAD Simulation for CMOS Nanoeletronic Devices

New York: Springer, 2017. — 337 p.This book demonstrates how to use the Synopsys Sentaurus TCAD 2014 version for the design and simulation of 3D CMOS (complementary metal–oxide–semiconductor) semiconductor nanoelectronic devices, while also providing selected source codes (Technology Computer-Aided Design, TCAD). Instead of the built-in examples of Sentaurus TCAD 2014, the practical cases presented here, based on years of teaching and research experience, are used to interpret and analyze simulation results of the physical and electrical properties of designed 3D CMOSFET (metal–oxide–semiconductor field-effect transistor) nanoelectronic devices.
The book also addresses in detail the fundamental theory of advanced semiconductor device design for the further simulation and analysis of electric and physical properties of semiconductor devices. The design and simulation technologies for nano-semiconductor devices explored here are more practical in nature and representative of the semiconductor industry, and as such can promote the development of pioneering semiconductor devices, semiconductor device physics, and more practically-oriented approaches to teaching and learning semiconductor engineering.
The book can be used for graduate and senior undergraduate students alike, while also offering a reference guide for engineers and experts in the semiconductor industry. Readers are expected to have some preliminary knowledge of the field.About the book (Modify by author Yung-Chun Wu).
Introduction of Synopsys Sentaurus TCAD Simulation.
Introduction.
Introduction of Moore’s Law and FinFET.
Sentaurus Window Environment and Workbench for TCAD Task Management.
Synopsys Sentaurus TCAD Software and Working Environment.
Simulation Project View on Sentaurus Workbench (SWB).
Sentaurus Visual.
Calibration and Services.
2D MOSFET Simulation.
3D FinFET with Lg = 15 nm and L_g = 10 nm Simulation.
Inverter and SRAM of FinFET with L_g = 15 nm Simulation.
Gate-All-Around (GAA) NWFET with L_g = 10 nm Simulation.
Junctionless FET with Lg = 10 nm Simulation.
Steep Slope Tunnel FET Simulation.
Extremely Scaled Si and Ge to L_g = 3-nm FinFETs and L_g = 1-nm Ultra-Thin Body Junctionless FET Simulation.
Foreword.
Design Guideline of Sub-20-nm to 9-nm Gate Length Si FinFET of Wine-Bottle Channel.
Study of Silicon L_g = 3-nm Bulk IM, AC, and JL FinFET.
Study of Germanium L[i]g = 3-nm Bulk FinFET.
Study of Silicon and Germanium UTB-JL—FET with Ultra-Short Gate Length = 1 and 3 nm[/i].Appendix: Synopsys Sentaurus TCAD 2014 Version Software.
Installation and Environmental Settings.