Voldman S.H. ESD: Circuits and Devices

2nd edition. — John Wiley & Sons, Ltd, 2015. — 544 p. — ISBN: 9781118954461.ESD: Circuits and Devices 2nd Edition provides a clear picture of layout and design of digital, analog, radio frequency (RF) and power applications for protection from electrostatic discharge (ESD), electrical overstress (EOS), and latchup phenomena from a generalist perspective and design synthesis practices providing optimum solutions in advanced technologies.
New features in the 2nd edition:
Expanded treatment of ESD and analog design of passive devices of resistors, capacitors, inductors, and active devices of diodes, bipolar junction transistors, MOSFETs, and FINFETs.
Increased focus on ESD power clamps for power rails for CMOS, Bipolar, and BiCMOS.
Co-synthesizing of semiconductor chip architecture and floor planning with ESD design practices for analog, and mixed signal applications
Illustrates the influence of analog design practices on ESD design circuitry, from integration, synthesis and layout, to symmetry, matching, inter-digitation, and common centroid techniques.
Increased emphasis on system-level testing conforming to IEC 61000-4-2 and IEC 61000-4-5.
Improved coverage of low-capacitance ESD, scaling of devices and oxide scaling challenges.
ESD: Circuits and Devices 2nd Edition is an essential reference to ESD, circuit & semiconductor engineers and quality, reliability &analysis engineers. It is also useful for graduate and undergraduate students in electrical engineering, semiconductor sciences, microelectronics and IC design.About the Author.

Electrostatic Discharge.
Electricity and Electrostatic Discharge.
Fundamental Concepts of ESD Design.
ESD, EOS, EMI, Electromagnetic Compatibility, and Latchup.
ESD Models.
ESD and System-Level Test Models.
Time Constants.
Capacitance, Resistance, and Inductance and ESD.
Rules of Thumb and ESD.
ESD Scaling.
Lumped versus Distributed Analysis and ESD.
ESD Metrics: Chip-Level ESD Metrics and Figures of Merit.
ESD Quality and Reliability Business Metrics.
Twelve Steps to Building an ESD Strategy.
Summary and Closing Comments.Design Synthesis.
Synthesis and Architecture of a Semiconductor Chip for ESD Protection.
Electrical and Spatial Connectivity.
ESD, Latchup, and Noise.
Interface Circuits and ESD Elements.
ESD Power Clamp Networks.
ESD Rail-to-Rail Networks.
Guard Rings.
Pads, Floating Pads, and No-connect Pads.
Structures under Bond Pads.
Mixed Signal Architecture: CMOS.
MS Architecture: Digital, Analog, and RF Architecture.
Digital-to-Analog Interdomain Signal Line Failures.
Summary and Closing Comments.MOSFET ESD Design.
Basic ESD Design Concepts.
ESD MOSFET Design: Channel Length.
N-Channel MOSFET Design: Channel Width.
ESD MOSFET Design: Contacts.
ESD MOSFET Design: Metal Distribution.
ESD MOSFET Design: Silicide Masking.
ESD MOSFET Design: Series Cascode Configurations.
ESD MOSFET Design: Multifinger MOSFET Design—Integration of Coupling and Ballasting Techniques.
ESD MOSFET Design: Enclosed Drain Design Practice.
ESD MOSFET Interconnect Ballasting Design.
ESD MOSFET Design: Source and Drain Segmentation.
MOSFET Design for Analog Applications.
Summary and Closing Comments.ESD Design: Diode Design.
ESD Diode Design: ESD Basics.
ESD Diode Anode Design.
ESD Diode Design: Interconnect Wiring.
ESD Design: Polysilicon-Bound Diode Designs.
N-Well Diode Design.
N+/P Substrate Diode Design.
ESD Design: Diode String Design.
Triple-Well ESD Diode Design.
Summary and Closing Comments Problems.
ESD Design: Passive Resistors.
N-Well Resistors.
N-Diffusion Resistor Design.
P-Diffusion Resistor Design.
BR.
Summary and Closing Comments.Passives for Digital, Analog, and RF Applications.
Analog Design Layout Revisited.
Common Centroid Design.
Interdigitation Design.
Common Centroid and Interdigitation Design.
Passive Element Design.
Resistor Element Design.
Capacitor Element Design.
Inductor Element Design.
Summary and Closing Comments.Off-Chip Drivers and ESD.
Off-chip Drivers.
OCDs: MVI.
OCDs: Self-Bias Well OCD Networks.
Programmable Impedance OCD Network.
OCDs: Universal OCDs.
OCDs: Gate-Array OCD Design.
OCDs: Gate-Modulated Networks.
OCDs ESD Design: Integration of Coupling and Ballasting Techniques.
Substrate-Modulated Resistor-Ballasted MOSFET.
Summary and Closing Comments.Receiver Circuits.
Receivers and ESD.
Receivers and ESD.
Receivers and Receiver Evolution.
Receiver Circuits with Pseudozero VT Half-Pass TG.
Receiver with ZVT TG.
Receiver Circuits with Bleed Transistors.
Receiver Circuits with Test Functions.
Receiver with Schmitt Trigger Feedback Network.
Bipolar Transistor Receivers.
Differential Receivers.
CMOS Differential Receiver with Analog Layout Concepts.
Summary and Closing Comments.Silicon on Insulator (SOI) ESD Design.
Silicon on Insulator ESD Design Concepts.
SOI Design MOSFET with Body Contact: Т-Shape Layout Style.
SOI Lateral Diode Structure.
SOI BR Elements.
Dynamic Threshold SOI MOSFET.
SOI Dual-Gate MOSFET.
SOI ESD Design: Mixed Voltage Т-Shape Layout Style.
SOI ESD Design: Mixed Voltage Diode Strings.
SOI ESD Design: Double-Diode Network.
Bulk to SOI ESD Design Remapping.
SOI ESD Design in MVI Environments.
Comparison of Bulk to SOI ESD Results.
SOI ESD Design with Aluminum Interconnects.
SOI ESD Design with Copper Interconnects.
SOI ESD Design with Gate Circuitry.
SOI FinFET Structure.
Summary and Closing Comments.ESD Circuits: BiCMOS.
Bipolar ESD Input Circuits.
Diode-Configured Bipolar ESD Input Circuits.
Bipolar ESD Input Circuits: Voltage-Triggered Elements.
BiCMOS Mixed Signal Designs.
Summary and Closing Comments.ESD Power Clamps.
ESD Power Clamp Design Practices.
Design Synthesis of ESD Power Clamps Trigger Networks.
Design Synthesis of ESD Power Clamp: The ESD Power Clamp Shunting Element.
ESD Power Clamp Issues.
ESD Power Clamp Design.
Master/Slave ESD Power Clamp Systems.
Series-Stacked RC-Triggered ESD Power Clamps.
ESD Power Clamps: Triple-Well Series Diodes as Core Clamps.
Summary and Closing Comments.Bipolar ESD Power Clamps.
Bipolar ESD Power Clamps.
Bipolar Voltage-Triggered ESD Power Clamps.
ESD Power Clamp Design Synthesis: Bipolar ESD Power Clamps.
Mixed Voltage Interface Forward-Bias Voltage and BVCEO Breakdown Synthesized Bipolar ESD Power Clamps.
Ultralow-Voltage Forward-Biased Voltage-Trigger BiCMOS ESD Power Clamp.
Bipolar ESD Power Clamps with Frequency Trigger Elements: Capacitance Triggered.
Summary and Closing Comments.Silicon-Controlled Rectifier Power Clamps.
ESD Silicon-Controlled Rectifier Circuits.
Lateral Diffused MOS Circuits.
DeMOS Circuits.
Ultrahigh-Voltage LDMOS (UHV-LDMOS) Circuits.
Summary and Closing Comments.Glossary of Terms.
Standards.
Index.