New York: Springer, 2017. — 173 p.
This book introduces readers to the potential of charge-sharing (CS) successive approximation register (SAR) analog-to-digital converters (ADCs), while providing extensive analysis of the factors that limit the performance of the CS topology. The authors present guidelines and useful techniques for mitigating the limitations of the architecture, while focusing on the implementation under restricted power budgets and voltage supplies.
ADCs for Low-Voltage Low-Power Applications
Review of SAR ADC Switching Schemes
Effects of Nonidealities on the Performance of CS-ADCs
Noise-Aware Synthesis and Optimization of Voltage Comparators
An 8-Bit 0.35-V CS-ADC with Comparator Offset Auto-Zero and Voltage Boosting
A 9-Bit 0.6-V CS-ADC with a MOSCAP-DAC
Conclusions and Future Work