Mohamed K.S. IP Cores Design from Specifications to Production. Modeling, Verification, Optimization, and Protection

Springer, 2016. — 162.This book discusses the life cycle process of IP cores from specification to production which includes four major steps: (1) IP modeling, (2) IP verification, (3) IP optimization, and (4) IP protection. Moreover, the book presents most of the famous memory cores and controller IPs and analyzes the trade-off between them. In this book, we give an in-depth introduction to SoC buses and peripheral IPs. We explain their features and architectures in detail. Moreover, we provide a deep introduction to Verilog from both implementation and verification points of view. The book presents a simple methodology in building a reusable RTL verification environment using UVM. UVM is a culmination of well-known ideas and best practices. Moreover, it presents simple steps to verify an IP and build an efficient and smart verification environment. A SoC case study is presented to compare traditional verification with a UVM-based verification. Bug localization is a process of identifying specific locations or regions of source code that is buggy and needs to be modified to repair the defect. Bug localization can significantly reduce human effort and design cost. In this book, a novel automated coverage- based functional bug localization method for complex HDL designs is proposed, which significantly reduces debugging time. The proposed bug localization methodology takes information from regression suite as an input and produces a ranked list of suspicious parts of the code. We present an online RTL-level scan-chain methodology to reduce debugging time and effort for emulation. Run-time modifications of the values of any of the internal signals of the DUT during execution can be easily performed through the proposed online scan-chain methodology. A utility tool has been developed to help ease this process.IP Cores Design from Specifications to Production: Modeling, Verification, Optimization, and Protection
Analyzing the Trade-off between Different Memory Cores and Controllers
SoC Buses and Peripherals: Features and Architectures
Verilog for Implementation and Verification
New Trends in SoC Verification: UVM, Bug Localization, Scan-C0068ain-Based Methodology, GA-Based Test Generation
Conclusions